Controlling PDN Resistance in PCB Design

What is PDN?

A Power Delivery Network (PDN) is the entire electrical path that delivers power from the voltage regulator (VRM) to the transistors inside a chip. It includes:

• PCB power planes and traces
• Package power/ground layers
• On-die power grid
• Vias, bumps, and connectors
• Decoupling capacitors at various levels

Think of the PDN as the “circulatory system” of an electronic device. Just as the circulatory system is responsible for supplying oxygen and nutrients to every cell of every organ in our body using arteries, veins, and capillaries, similarly, the job of PDN is to deliver clean, stable voltage to every transistor through traces, planes, and vias, under all conditions and situations.

Why Keeping PDN Resistance Low is Critical?

The performance and health of a PDN is strictly defined by the effective resistance of the pathways between the voltage source and the loads. This resistance must be kept as low as possible. Let's analyze how keeping the path resistance low is advantageous.

1. Helps minimize IR Drop

On a functional PCB-based system, when the load ICs draw current I from a voltage source (VRM) with supply voltage V, this current flows through all parts of the PDN. Let the resistance of the path between the VRM and the load be R, where R is the combined DC resistance of all the vias, traces, and planes between the VRM (source) and the load (sink).  The voltage drop in the path is given by:

Vd = I⋅R

Now the net voltage available at the load (Vl) is:

Vl = V - Vd = V - I.R

As chips draw more current, even tiny resistances cause a significant voltage drop.   Every IC needs a specific value of the DC with a small tolerance for its function. These details are provided in the datasheet by the chip manufacturer (Vendor). If the voltage at the transistor dips below these specs, you may face:

• Timing failures
• Logic errors
• Reduced performance
• System crashes

2. Helps reduce Power Losses

Whenever current passes through a resistance, there is a power loss. This power wasted as heat is given by the formula:

P=I2⋅R

We can reduce these power losses either by reducing the amount of current flowing through the pathways or by reducing the resistance of the path. Since the current is solely dependent on the load ICs selected for a function. There is nothing we can do much about it. We can only try to improve and control the resistance of the path because:

Lower resistance → less heat → better efficiency and reliability.

Techniques to Keep PDN Resistance Low

The resistance of a conductor is defined by the formula:

R = p L/A , where

• p is the resistivity of the conductor, which depends upon the type of conductor material
• L is the length of the material and
• A is the area of the cross-section of the material.

Since the path of PCB-based PDN consists of traces, planes, and vias, we can always control the geometry of power traces, planes, and vias to keep their lengths small and the area of cross-section large to keep the resistance of the PDN as low as possible.  Here are some basic design techniques to adopt.

1. Use wide and thick Power/Ground planes

Make sure that you use solid power planes to carry the power from the source to the sinks. The Cu planes provide a larger area for the current to flow and hence reduce the resistance. In case we cannot have solid planes, make sure you use wider traces to carry the current to the IC pins. At all locations of the path, the width of the power trace should be wide enough to carry the required amount of current. There are online calculators that can be used to calculate the width of the Cu traces required to carry the amount of the load current. 

We can take care of this important issue right at the stage of the stack-up definition. We can plan and reserve some layers to serve as planes for power and GND nets distribution, and keep their thickness higher than the signal layers. For example, if the normal signal layers in the stack-up are 1 Oz, then keep the power layer thickness to 2 Oz and design the stack-up accordingly. So, below are the simple rules to follow to keep the PDN resistance low:

• Wider copper traces reduce resistance.
• Thicker copper layers (e.g., 2 oz instead of 1 oz) for Pwr/GND nets also help reduce the PDN resistance.
• Solid planes are preferred over narrow traces.

2. Add Multiple Vias (Via Arrays)

In dense designs, it is no longer possible to route the power signals from the source to the sink in one layer. We have to switch layers in between. Oftentimes, the designers ignore the ampacity of the power path while making transitions from one layer to the other. They have enough Cu on both layers, but forget the amount of Cu in the vertical direction connecting the two horizontal layers. This vertical path connecting the two planes on two different layers consists of the vias that connect the two layers while carrying the current from one layer and transferring it to the other layer, as shown below in the picture. We should always be aware of the ampacity of the power being used. The resistance and ampacity of a via depend on the diameter of the via, pad sizes, the plating thickness of the Cu on the inner walls of the via, and the depth of the via.

There are plenty of online calculators available that can be used to do these calculations by PCB designers. For example, if we are using a power via that can carry a max of 0.75 A, and we are using these vias for a voltage rail carrying 2A of current. Then make sure that we use AT LEAST 3 power vias every time we make a transition between two layers. Using more than 3 vias is always preferred and better.  Using multiple vias is actually like multiple resistances in parallel, where the resultant resistance is reduced by the factor of the number of resistances.

1/Re = 1/R + 1/R + 1/R => Re = R/3

Using many vias in parallel reduces total resistance and inductance.

3. Use Multiple Power/Ground Layers

In modern-day designs, the high density of the functions and the logic has led to high current rails. Sometimes it is difficult to supply this huge amount of current through a single plane. In such scenarios, we allocate multiple layers in the stackup for such high current rails. Stacking several layers in parallel lowers resistance and improves current-carrying capacity.

4. Shorter Power Paths

Since the resistance of the PDN path strictly depends upon the length of the path between the source and the sink. In a complete picture, the length of this path, all the way from VRM to the die power/gnd pins, is categorized as follows:

• VRM → PCB
• PCB → package
• Package → die

Design Architects, Manufacturing equipment companies, Innovative Technology, and Layout engineers are all working together to develop a supporting methodology at all stages to minimize the distance between the source (VRMs) and sinks (LOAD) to reduce resistance.

5. Use Low-Resistance Materials

Material scientists are working all out to develop high-quality conductor materials and low-resistivity alloys to ensure low resistance for the PDN paths on PCBs, inside chip packages, and dies. Components are shrinking in size, and PCB layout pictures are shifting to HDI realms to reduce the paths that electrons have to travel from source to sink, which is helping a lot to reduce and keep the PDN resistance as low as possible. Some advanced packages even use copper pillars or embedded rails.

6. Optimized Package Power Grid

Advanced packaging techniques:

• Flip-chip bumps
• Redistribution layers (RDL)
• Power rings and mesh grids
• Embedded power rails

These reduce resistance between the package and the die.

7. Use of Power Integrity Simulation Tools

Tools like:

• Ansys SIwave
• Cadence Sigrity
• Keysight ADS

help optimize PDN resistance and impedance before manufacturing.

In Short

A low-resistance PDN is essential because:

• It prevents voltage droop
• Reduces heat
• Improves reliability

And designers can achieve this through:

• Wide/thick copper planes
• Via arrays
• Multiple power layers
• Short power paths
• High-quality materials
• Advanced packaging