SMTA Announces Wafer-level Packaging Symposium Program will be Held from February 14 to 16, 2023

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The SMTA has announced the accepted speakers for the Wafer-Level Packaging Symposium (WLPS) that will be held February 14-16, 2023 at the Marriott Fremont Silicon Valley in Fremont, California. The Wafer-Level Packaging Symposium will bring together the semiconductor industry’s most respected authorities to address all aspects of wafer-level, 3D device packaging, advanced manufacturing & test technologies. 

Addressing wafer-level packaging, 3D, and Advanced Manufacturing & Test technologies, the Wafer-Level Packaging Symposium will be at the forefront of packaging technology evolution. The conference will feature attendees from around the globe in the heart of Silicon Valley to immerse themselves in the latest technology and business trends.

Packaging technology expert John Lau, Ph. D., will kick off the program Tuesday afternoon with a Professional Development Course on February 14, 2023. The lecture course is titled, “Advanced Packaging: Fan-out, Chiplet, and Heterogeneous Integration”. 

The Technical Program consists of over 20 presentations addressing wafer-level packaging (WLP), 3D packaging, and advanced manufacturing and test technologies. The program will conclude with a “Wafer-Level versus Panel Level” panel discussion moderated by Jan Vardaman.

Registration for WLPS is now available online. Discounted rates are available for conference registration made on or before Wednesday, January 25, 2023. All presentations along with the PDC are included in standard registration this year.

Click here to learn more about the program.