Cadence’s Integrity 3D-IC Platform Receives Certification for TSMC’s 3DFabric Technologies

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Cadence Design Systems, announced the leading Cadence^® Integrity^™ 3D-IC platform has achieved certification for and met all reference design flow criteria for TSMC’s 3DFabric^™ offerings, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS^®) and System-on-Integrated-Chips (TSMC-SoIC^™) technologies. As part of the collaboration, the companies worked together to enable Cadence’s support of the TSMC 3Dblox^TM standard to help customers accelerate advanced multi-die package design across 5G, AI, mobile, hyper-scale computing and IoT applications.

The Cadence Integrity 3D-IC platform combines system planning, implementation, Cadence Allegro^® X packaging technologies and system-level analysis and is the industry’s leading full-flow platform enabled for TSMC’s new 3Dblox standard, which speeds 3D front-end design partitioning in complex systems. 3Dblox streamlines key aspects of design methodologies and allows chipset reuse, providing a seamless interface for Cadence system analysis tools for early power delivery network (PDN) and thermal analysis via the Cadence Voltus^™ IC Power Integrity Solution and Celsius^™ Thermal Solver, extraction and static timing analysis via the Cadence Quantus^™ Extraction Solution and Tempus^™ Timing Signoff Solution and system-level layout versus schematic (LVS) checks via the Cadence Pegasus^™ Verification System. Cadence’s new Allegro Substrate Router (ASR) technology is integrated with Allegro X packaging technologies for ultra-high-density die-to-die and die-to-package RDL auto-routing.

“In today’s electronics market, customers need every advantage they can get when developing the highly sophisticated 3D-ICs that power emerging application areas,” said Dan Kochpatcharin, head of the Design Infrastructure Management Division at TSMC. “By working to ensure the Cadence Integrity 3D-IC platform is certified for use with TSMC 3DFabric technologies, our mutual customers can enjoy significant gains in design efficiency that will help them get advanced, multi-chip solutions to market quickly.”

“Our Integrity 3D-IC platform offers system planning, packaging and system-level analysis in a single platform, which provides customers with seamless design creation capabilities and a comprehensive signoff flow that supports TSMC’s 3DFabric offerings,” said Dr Chin-Chi Teng, senior vice president and general manager in the Digital & Signoff Group at Cadence. “By continuing to collaborate with TSMC, we’re giving our customers an efficient way to leverage the latest developments in 3D chip and multi-die technologies without compromising on time to market.”

The Cadence Integrity 3D-IC platform is part of the company’s broader 3D-IC offering and aligns with the Cadence Intelligent System Design^™ strategy, enabling system-on-chip (SoC) design excellence.

Click here to learn more about Cadence Integrity 3D-IC Platform.