Cadence and TSMC Collaborate to Accelerate 3D-IC Multi-Chiplet Design Innovation

https://cdn.pcbdirectory.com/news/46D4D250_3E04_48E0_B2D4_B40E14C5778C_637709106955945668.jpg712370

Cadence Design Systems has announced that it is working with TSMC to accelerate 3D-IC multi-chiplet design innovation. As part of the collaboration, the Cadence® Integrity™ 3D-IC platform is enabled for TSMC 3DFabric™ technologies. Cadence® Integrity™ 3D-IC platform is the industry’s first unified platform for 3D-IC planning, implementation, and system analysis while TSMC 3DFabric™ technologies is TSMC’s comprehensive family of 3D silicon stacking and advanced packaging technologies.

In addition, the Cadence Tempus™ Timing Signoff Solution has been enhanced to support a new stacking static timing analysis (STA) signoff methodology, shortening design turnaround time. Through these latest milestones, customers can confidently adopt the Cadence 3D-IC solution and TSMC’s 3DFabric technologies to create competitive hyperscale computing, mobile, and automotive applications.

The Cadence 3D-IC solution supports TSMC’s full set of 3D silicon stacking and advanced packaging technologies, including Integrated Fan-Out (InFO), Chip-on-Wafer-on-Substrate (CoWoS®), and System-on-Integrated-Chips (TSMC-SoIC™). The 3D-IC solution also aligns with the Cadence Intelligent System Design™ strategy, driving system-on-chip (SoC) design excellence.

The Cadence Integrity 3D-IC platform provides 3D chip and package planning, implementation, and system analysis in a single, unified cockpit. This lets customers streamline multi-chiplet design planning, implementation, and analysis of 3D silicon stacking while also optimizing engineering productivity, power, performance, and area (PPA). Also, the platform has co-design capabilities integrated with the Cadence Allegro® packaging technologies and the Cadence Virtuoso®'s platform, enabling complete 3D integration and packaging support. 

Click here to learn more about the Cadence Integrity 3D-IC Platform.